1. Technical Field
The present disclosure relates to structures of insulated-gate transistors, for example, MOS transistors. More specifically, the present disclosure relates to a method for manufacturing such a transistor providing a step of adjustment of the transistor threshold voltage.
2. Description of the Related Art
Many MOS transistors manufacturing methods are known. To decrease transistor dimensions, it has been provided to replace the gate insulator of the MOS transistors with insulators of high dielectric constant. It has also been provided to adjust the threshold voltage of such transistors, at the end of the manufacturing of their insulated gates, by performing a controlled anneal, which enables the diffusion of atoms modifying this threshold voltage.
FIG. 1 schematically illustrates such a method. In the upper portion of a semiconductor substrate 10 are formed insulating trenches 12 which enable to insulate the different electronic components formed at the surface of substrate 10 from one another. For example, in the case of MOS transistors, trenches 12 delimit the channel regions of the transistors.
Trenches 12 generally are trenches known as “STI”, for Shallow Trench Isolation, formed of silicon oxide. In practice, the insulating trenches are formed by etching of the upper surface of semiconductor substrate 10 and deposition of an insulating material in the openings defined by etching. A polishing, for example, a chemical-mechanical polishing (CMP), is then performed to only leave the insulating material in the openings.
Insulated gate T of a MOS transistor, formed at the surface of a channel region delimited by trenches 12, comprises a stack of several insulating layers, topped with several conductive layers.
In the shown example, this gate comprises a stack of a first insulating layer 14, of a second heavily-insulating layer 16, of a layer 18 of a material having atoms capable of diffusing towards the insulating material, of a layer of a conductive material 20, and of an upper conductive layer 22 on which is taken the transistor gate contact.
Conventionally, first insulating layer 14, as close as possible to semiconductor substrate 10, is made of silicon oxide or of silicon oxynitride. This layer is provided to obtain a good interface with the semiconductor material of substrate 10, and generally has a small thickness, on the order of one nanometer. Heavily-insulating layer 16 is made of a material having a high dielectric constant (known as “high-K”). Among such high-K materials, hafnium oxide (HfO2) or hafnium oxynitride (HfSiON) can for example be mentioned. Other high-K alloys are known.
Layer 18 performs a specific function to adjust the transistor threshold voltage. This layer may for example be made of lanthanum, of aluminum, of magnesium, of dysprosium, or more generally of a material from the category of rare earths, or of an alloy comprising one or several of these materials. When the structure is annealed, lanthanum, aluminum, magnesium, dysprosium atoms of layer 18 diffuse towards the interface between insulating layers 14 and 16 to form a silicate, for example, a lanthanum silicate. This diffusion enables to adjust the transistor threshold voltage, since the material having diffused generates dipoles at the interface between layers 14 and 16, which modify this threshold voltage. The threshold voltage adjustment depends on the thickness of diffusion layer 18, on the anneal duration and temperature of the structure.
The upper layers 20 and 22 of the insulated gate are layers conventional in the forming of MOS transistors, and will not be detailed any further herein. As an example, layer 20 may be made of a metal such as titanium nitride and layer 22 may be made of polysilicon.
In the case of an association of MOS transistors of different types on a same substrate, different gate structures are generally provided for these transistors, the diffusing layer being placed in the gate stack at different levels for a proper adjustment of the threshold voltage.